As one of scaling technologies for increasing the density of a semiconductor device, a multi-gate transistor has been proposed, in which a fin-shaped silicon body is formed on and protrudes from a substrate and a gate is formed on the silicon body.
Since a three-dimensional channel is used in the multi-gate transistor, scaling can be achieved. In addition, current control capacity can be improved without increasing a gate length of the multi-gate transistor. In addition, a short channel effect (SCE), in which the electric potential of the channel region is affected by the drain voltage, can be effectively reduced or suppressed.